1. Field of the Invention
The present invention relates to a wiring substrate having top-flattened solder bumps projecting from the main surface thereof, and to a method for manufacturing the same.
2. Description of the Related Art
A known wiring substrate includes a resin dielectric layer and a conductor layer formed in a predetermined pattern on the resin dielectric layer. An example of such a wiring substrate is shown in FIG. 5, which is an enlarged partially broken away, sectional view of a substrate 101 and which shows a portion located on the side toward the main surface. The substrate 101 has a core substrate (resin dielectric layer) 103 at its center. One or more resin dielectric layers 105 are formed in layers on either side of the core substrate 103, and a solder resist layer (resin dielectric layer) 107 is formed on the dielectric layer 105 on one side of the core substrate 103, thereby providing the main surface of the substrate 101.
A plurality of substantially cylindrical through-hole conductors 111 are formed in the core substrate 103 at predetermined positions and are filled with respective resin fillers 112. A plurality of through-holes 113 which enable the formation of vias are formed in the resin dielectric layer 105 at predetermined positions, and via conductors 115 are formed in the corresponding through-holes 113. A plurality of openings 117 which provide exposure of respective pads 116 are formed in the solder resist layer 107 at predetermined positions. Further, a first conductor layer 118 including wiring lines and pads is formed in a predetermined pattern between the core substrate 103 and the resin dielectric layer 105 and is connected to the through-hole conductors 111 formed in the core substrate 103 and the via conductors 115 formed in the resin dielectric layer 105. In addition, a second conductor layer 119 including wiring lines and pads is formed in a predetermined pattern between the resin dielectric layer 105 and the solder resist layer 107 and is connected to the via conductors 115. When a plurality of the resin dielectric layers 105 are formed, a conductor layer (not shown) is provided between the resin dielectric layers corresponding to layer 105.
In the substrate 101, bumps are formed of, for example, solder or gold on the corresponding pads 116 formed in the solder resist layer 107, so as to serve as terminals for electrical connection. Further, in order to ensure connection to an electronic component (e.g., an IC chip, a chip capacitor, a chip resistor, or the like) to be mounted on the substrate 101, the bumps are flattened at their tops by use of a flat pressing surface, thereby forming top-flattened solder bumps corresponding to bump 120.
Because the substrate 101 uses a resin layer of substantially uniform thickness as the resin dielectric layer 105, portions of the resin dielectric layer 105 located above the first conductor layer 118 present between the core substrate 103 and the resin dielectric layer 105 rise slightly. In the course of forming the resin dielectric layer 105, the resin dielectric layer 105 is pressed while being heated, and thus the surface of the resin dielectric layer 105 is flattened to a certain extent. However, for example, as shown in FIG. 6, a portion of the resin dielectric layer 105 which is formed on a solid layer 121 (which is a portion of the first conductor layer 118 and extends over a certain area) unavoidably rises to a certain extent in relation to the remaining portion of the resin dielectric layer 105. As a result, a first pad 116B, which is located within a region which is formed by projecting the solid layer 121 toward the main surface (hereinafter simply referred to as a xe2x80x9cregion above the solid layerxe2x80x9d) is formed at a raised position whereas a second pad 116C is located outside the region above the solid layer. Thus, as represented by dotted lines in FIG. 6, the solder bump 122B formed on the first pad 116B and the solder bump 122C formed on the second pad 116C are of the same size, but differ slightly in the position of the vertex, i.e., bump 122B projects outwardly from substrate 101 slightly more than bump 122C. These solder bumps 122B and 122C are flattened at their tops through pressing, through the use of a common, flat pressing surface 123, and are thus formed into a first top-flattened solder bump 120B and a second top-flattened solder bump 120C, respectively. Since the difference in the positions of the vertices of the bumps 122B and 122C results in a difference in the amount of solder to be crushed in the course of the flattening process, the diameter M1 of the top face of the top-flattened solder bump 120B is greater than the diameter M2 of the top face of the top-flattened solder bump 120C, as shown in FIG. 6. Actual measurements have revealed that a difference of 2 to 3 xcexcm in positional height between the pads 116 leads to a difference of about 10 xcexcm in top face diameter between the top-flattened solder bumps 120.
It will be appreciated that the connection terminals of an electronic component to be mounted on the substrate 101 are formed in a very uniform fashion, and that the fact that the top-flattened solder bumps 120 of the substrate 101 differ in top face diameter can, in some cases, result in variations in connection accuracy among the connections when the electronic component is mounted on the substrate 101.
An object of the invention is to provide an improved wiring substrate in which top-flattened solder bumps have substantially the same top face diameter irrespective of the presence of a solid layer, and to thereby improve the accuracy of the connections between the wiring substrate and an electronic component mounted thereon.
Another object of the present invention is to provide a method for manufacturing the improved wiring substrate.
According to one aspect of the invention, in order to achieve the above objects, the present invention provides a method for manufacturing a wiring substrate having a main surface, a back surface, and a plurality of top-flattened solder bumps projecting from the main surface. The method comprises the steps of: forming a solid layer on a core substrate so as to partially cover the core substrate; forming at least one resin dielectric layer on the solid layer and the core substrate; forming a plurality of pads on the resin dielectric layer in such a manner that the plurality of pads are exposed at the main surface of the wiring substrate, the pads including first pads located within a region above the solid layer and second pads located outside of the region; applying, through printing, solder paste onto the plurality of pads such that the amount of solder paste applied onto each of the first pads is smaller than that applied onto each of the second pads; melting the applied solder paste, through reflowing, so as to form substantially hemispherical solder bumps; and flattening top portions of the substantially hemispherical solder bumps through pressing of a flat pressing surface against the top portions, thereby forming the top-flattened solder bumps.
According to an important feature of the present invention, solder paste is applied through printing onto a plurality of pads which are exposed at the main surface so that the solder paste can be applied thereto. Next, the applied solder paste is melted to obtain the substantially hemispherical solder bumps. Subsequently, the aforementioned flat pressing surface is pressed against top portions of the solder bumps so as to obtain the top-flattened solder bumps. Relative to the solder paste application step, each pad is classified as first pad or second pad in accordance with whether or not the pad is located within the region above the solid layer and, as indicated above, a pad is classified as first pad when the pad is located within the region above the solid layer, and as a second pad when the pad is located outside the region. A key feature is that the amount of solder paste applied onto the first pads is smaller than that of solder paste applied onto the second pads.
Generally, the overall thickness of a wiring substrate increases at a portion where a solid layer is sandwiched between layers, as compared with a portion where such a solid layer is absent. As a result, when solder bumps are to be top-flattened by use of a common flat pressing surface, the distance (vertical spacing) between the first pads and the flat pressing surface is shorter or smaller than that between the second pads and the flat pressing surface. In other words, after the flattening step, in terms of the height of a given solder bump above a corresponding pad, the solder bumps formed on the corresponding first pads are lower or shorter than those formed on the second pads. As a consequence, when solder paste is applied in the same amount onto both the first and second pads, because the solder bumps formed on the corresponding first pads are pressed downward to a greater extent than, and thus are shorter than, those formed on the second pads, the solder bumps formed on the first pads have a top face greater in diameter than the top face of the solder bumps formed on the second pads.
In contrast, according to the present invention, since the amount of the solder paste applied to each of the first pads is smaller than that of the solder paste applied onto each of the second pads, the solder bumps formed on the corresponding first pads are smaller in size than those formed on the second pads, thereby reducing the difference in top face diameter between first top-flattened solder bumps formed on the corresponding first pads and second top-flattened solder bumps formed on the corresponding second pads. Therefore, when an electronic component is mounted on a wiring substrate according to the present invention, the connection terminals of the electronic component are connected to the first pads and the second pads under similar conditions, irrespective of presence of the solid layer.
The aforementioned resin dielectric layer may be formed of any resin so long as the resin has substrate insulating properties. Examples of such a resin include an epoxy resin, a BT resin, and a composite material formed from resin, and glass fiber or ceramic powder, such as a glass-epoxy composite material. The solid layer is a conductor layer provided between resin dielectric layers while extending over a certain area. The metal used to form the solder bumps may be selected as appropriate in accordance with, for example, the material for the connection terminals of an electronic component to be mounted on the wiring substrate. Examples of such a metal include a Pbxe2x80x94Sn solder such as 90Pb-10Sn, 95Pb-5Sn, and 40Pb-60Sn; a Snxe2x80x94Sb solder; a Snxe2x80x94Ag solder; a Snxe2x80x94Agxe2x80x94Cu solder; an Auxe2x80x94Ge solder; and an Auxe2x80x94Sn solder. The flat pressing surface is preferably formed by use of a metallic material such as steel, or a ceramic material.
Each pad can be implemented in various forms including, for example, a pad-on-via (wherein a pad is provided on a via), or a pad-off-via (wherein a pad is provided off a via). Pads of different forms may be present on the same wiring substrate. Each via may assume the form of a filled via, which is filled with plating metal and has a flat top face, or an unfilled via, which is not completely filled with plating metal and is depressed at a central portion thereof.
The amount of solder paste to be applied onto a particular pad must be determined in consideration of the form of each pad and that of each via. For example, in the case of a pad associated with an unfilled via, the amount of solder paste depends on whether the pad is a pad-on-via or a pad-off-via. Certain wiring substrates may include pads of different areas (because of, e.g., openings of different diameters for exposure of the pads). Therefore, when the same wiring substrate includes pads of different forms or different sizes, the present invention must be applied to first and second pads of the same form and the same size, i.e., to first pads and to those second pads which are identical with the first pads in terms of form and size.
Preferably, the flattening step is adapted to form the top-flattened solder bumps such that the diameter of a top face of each of the first top-flattened solder bumps formed on the corresponding first pads is substantially equal to that of a top face of each of the second top-flattened solder bumps formed on the corresponding second pads.
According to the present invention, in the flattening step, the solder bumps are top-flattened such that the diameter of the top face of each first top-flattened solder bump formed on the corresponding first pad is substantially equal to that of the top face of each second top-flattened solder bump formed on the corresponding second pad. Therefore, in a subsequent step of mounting an electronic component on the wiring substrate, the first pads and the second pads are able to effect substantially the same state of connection to the connection terminals of the electronic component.
Preferably, a printing mask is used in the solder paste application step and has first through-holes corresponding to the first pads, and second through-holes corresponding to the second pads, the first and second through-holes being formed such that the diameter of the first through-holes is smaller than that of the second through-holes.
According to this aspect of the present invention, wherein the solder paste application step uses a printing mask having through-holes formed therein such that the diameter of through-holes corresponding to the first pads is smaller than that of through-holes corresponding to the second pads, even when solder paste is applied onto the first and second pads in a similar manner, the amount of solder paste to be applied onto each first pad through the printing mask is smaller than the amount of solder paste to be applied onto each second pad through the printing mask. Therefore, by virtue of the consequent reduction in the difference in top face diameter between top-flattened solder bumps that results from the presence or absence of a solid layer, there can be realized a reduction in the difference in quality of the connection between top-flattened solder bumps formed on the first pads and those formed on the second pads.
If top-flattened solder bumps can be provided which have substantially the same top face diameter, regardless of the presence/absence of a solid layer, in a subsequent step of mounting an electronic component on the wiring substrate of the invention, the first pads and the second pads can realize or achieve substantially the same state of connection to the connection terminals of the electronic component.
No particular limitation is imposed on the printing mask, so long as the printing mask has through-holes formed therein so as to allow solder paste to pass therethrough. Examples of such a printing mask include a screen mask, and a metal mask, i.e., a metal sheet, such as a stainless steel sheet, having holes formed therein.
In accordance with a further aspect of the present invention a wiring substrate is provided having a main surface, a back surface, and a plurality of top-flattened solder bumps projecting from the main surface, the wiring substrate comprising a core substrate; a solid layer formed on the core substrate and partially covering the core substrate; at least one resin dielectric layer formed on the solid layer and the core substrate; a plurality of pads formed on the resin dielectric layer and exposed from the main surface, the pads including first pads located within a region above the solid layer and second pads located outside of the region; and first top-flattened solder bumps formed on the corresponding first pads and second top-flattened solder bumps formed on the corresponding second pads. The diameter of a top face of each of the first top-flattened solder bumps is substantially equal to that of a top face of each of the second top-flattened solder bumps.
The wiring substrate of the present invention is configured such that solder bumps formed on the corresponding pads on the main surface assume substantially the same top face diameter irrespective of presence of the solid layer. Therefore, in a subsequent step in the manufacture of the wiring substrate in accordance with this aspect of the invention wherein an electronic component is mounted on the wiring substrate, the first pads and the second pads can achieve or realize substantially the same state of connection to the connection terminals of the electronic component.
Further features and advantages of the present invention will be set forth in, or apparent from, the detailed description of preferred embodiments thereof which follows.